Z80 buses, clock and pinout

The CPU uses address, data and control signals to communicate with memory and devices.

ADDRESS · DATA · CONTROL

A bus is a group of electrical lines that carries related information. The address bus selects a location. The data bus carries a byte. Control signals say what kind of transfer is happening and when devices should respond.

Inside the CPU

Open the architecture diagram to inspect the CPU blocks at a larger size. Select a labeled part to read its role.

Use the zoom buttons or drag the diagram after zooming in.

Three groups of signals

Bus or signal	Width / direction	Job
Address A15–A0	16 bits, CPU outputs	Selects a memory or I/O address. A 16-bit memory address can select 0000h–FFFFh: 65,536 byte locations.
Data D7–D0	8 bits, bidirectional	Carries one byte from memory or a device to the CPU, or from the CPU to them.
Control	Several individual lines	Signals read, write, memory, I/O, opcode fetch, refresh, interrupt, wait and bus control.
CLK	Input to CPU	Sets the timing reference. One clock period is one T-state. Instructions take a number of T-states.

The address does not travel on the data bus. A 16-bit address and an 8-bit data byte use separate pins.

Watch instructions use the clock

Choose an operation. Step or run through its clock periods. One clock period is one T-state.

LD A,(HL)PC fetches opcode 7Eh, then the CPU reads 2Ah from memory address 8000h into A.

Ready · 0 of 7 T-states

Address bus—

Data bus—

Control—

CPU statePC 0100h · A 00h

Press Step to advance one clock period.

With no WAIT states, this instruction takes 7 T-states: 4 for the opcode-fetch M1 cycle and 3 for the memory read. At 4 MHz, that is 1.75 μs.

The animation separates decode from bus timing to make each part clear. Real hardware overlaps some internal work. I/O cycles include one automatic wait state.

Follow a memory read

PC contains 0100h, so the CPU puts 0100h on A15–A0.
The CPU marks a memory read: MREQ and RD are asserted.
Memory places the byte at 0100h on D7–D0.
The CPU reads the opcode, advances PC and continues the instruction cycle.

A normal NOP takes 4 T-states. At a 4 MHz clock, one T-state is 0.25 microseconds and 4 T-states take 1 microsecond. Other instructions need different numbers of T-states.

Follow a memory write

Suppose HL contains 8000h and A contains 2Ah. An instruction such as LD (HL),A puts 8000h on the address bus and 2Ah on the data bus. It asserts MREQ and WR. Memory stores 2Ah at address 8000h.

The data bus changes direction: memory drives it during a read, and the CPU drives it during a write.

Read the Z80 pinout

Open the pinout to inspect it at a larger size. Select a signal name to highlight its pin and read its job.

The small bubbles mark active-low control pins. Address and data labels are clickable too.

Principal pins

Pin group	Examples	What to remember
Address	A0–A15	One 16-bit address is presented for each memory or I/O transfer.
Data	D0–D7	Eight bits move in either direction.
Memory and I/O	MREQ, IORQ	Select memory cycles or I/O cycles.
Read and write	RD, WR	Tell the selected device which direction to transfer data.
Opcode and refresh	M1, RFSH	M1 identifies an opcode-fetch cycle. RFSH marks a dynamic-memory refresh cycle.
Timing and wait	CLK, WAIT	CLK times the CPU. WAIT can extend a cycle when a device is not ready.
Interrupts	INT, NMI	Request service from the CPU. NMI cannot be disabled by the normal interrupt-enable control.
Bus control	BUSRQ, BUSAK	Allow another device to request and take control of the buses.
Other	RESET, HALT, VCC, GND	Reset initializes the CPU; HALT reports a halted state; VCC and GND power the chip.

A bar over a signal name means active-low: the signal is asserted near 0 volts. The diagram uses bubbles for active-low pins.